Lewis Sternberg
8005 NW Hawkins Blvd
Portland, OR 97229
(503) 464-0333
lewis_jobs at
star-mountain.com
Summary
Professional contractor. Motivated
top performer with excellent training, communication and interpersonal
skills. A proven track record in identifying
problems and developing innovative solutions.
Especially adept with analog/digital, hardware/software,
verification/design.
Professional Experience
Principal Contract Engineer Boeing Phantom Works, Kent, WA 2008
– present
·
Verification of a
rad-hard 49-processor IC
__________________________________
Principal Contract Engineer Mentor Graphics, Chandler, AZ 2007
·
Conversion of legacy testbench
to SystemVerilog for a set-top-box
SOC for a client of Mentor Graphics’ Design Services organization using Questa, AVM
__________________________________
Principal Contract Engineer Intel, Hillsboro, OR 2006
- 2007
·
Architect Multi-Cluster
Testbench for Larrabee (advanced graphics) project using Specman Elite
·
Architect and execute PCI-Express switch testbench
__________________________________
Principal Contract Engineer Texas Instruments , Dallas, TX 2006
·
Architected
module-level testbench using Specman
in extremely tight time-frame.
__________________________________
Principal Contract Engineer Xerox, Wilsonville, OR 2006
·
Develop Requirements,
Specification, and Test Plan for a low-cost high-speed serial bus for an
industrial environment
·
Execute lab tests and
document results
__________________________________
Principal Contract Engineer Intel, Hillsboro, OR
2004 - 2005
·
Create testbench for PCI-Express-like bus óRMII bus using eRM.
·
Modify legacy
Specman Elite testbench for reuse
with a Gigabit Ethernet MAC 10/100/1000T
·
Verified critical
initialization sequences and CSRs
·
1st silicon
fully functional
__________________________________
Senior Contract Engineer PMC-Sierra, Portland, OR
2003 - 2004
·
Verified SOC
core-bus optimization using Verilog and Specman Elite
·
Verified critical
initialization sequences
·
Optimized internal
tools for use with NC-Sim, Specman Elite, Simvision and Debussy
·
1st silicon
fully functional
Senior Contract Engineer Credence Systems Corp, Portland, OR
2003
·
Developed Analog
Mixed-Signal Verification Plan for 4GHz serdes full-custom IC.
·
Wrote Verilog-AMS
measurement modules and testbenches for critical-path analyses.
·
Developed and
documented core digital algorithm for serdes training sequence.
__________________________________
Senior Contract Engineer Teseda Corp, Portland, OR 2002
- 2003
·
Brought up and
verified circuit board with high-speed Altera FPGAs and CPLDs.
·
Wrote Verilog
code, simulated with ModelSim and synthesized in Mentor Graphics’
Leonardo for board production self-test.
·
Documented board test
usage and procedures.
__________________________________
Senior Contract Engineer IBM, Portland, OR 2001
- 2002
·
Verified 300,000 gate
block in a multi-million gate cache
coherency ASIC for an IA-64 based multi-processor system
using Specman Elite, e,
Verilog, and VHDL to ensure 1st silicon success.
·
Developed solutions to
test inter-partition messaging – bringing new functionality to the NUMA-Q
product line.
·
Pioneered methodology
to carry verification techniques into laboratory testing saving considerable
time and eliminating duplicated efforts.
__________________________________
Senior Engineer, Qualis Design Corporation, Portland, OR 1999
- 2001
·
Designed behavioral
models to allow IP integration in an ADSL
line card ASIC using Verilog, e,
Specman Elite.
·
Developed tests for a
terabit router to ensure architecture’s scalability (tcl, VHDL).
·
Opened new markets to
Qualis by expanding verification IP to include Analog-Mixed-Signal (VHDL-AMS).
·
Trained hundreds of
engineers on high-level verification methodologies using VHDL, Verilog.
·
Delivered papers to leading technical conferences
to increase Qualis’ presence and stature.
__________________________________
Senior Contract
Engineer, IMS, Virtual Test
Division, Portland, OR 1995
–1999
·
Made
Analog-Mixed-Signal virtual test a reality by creating simulation models of ICs
and testers.
·
Created library
products for development of DUT models in a variety of languages: SpectreHDL, MAST, Verilog, Verilog PLI, Skill, SPICE with Cadence’s Artist.
·
Modeled testers for
use in Dantes virtual test product: Teradyne,
Credence, and LTX.
__________________________________
Consultant, Analogy, Inc, Portland, OR 1994,
1997
·
Created tactical and
strategic competitive analysis of Analogy and Cadence products for a
comprehensive in-depth presentation to the annual Analogy global sales meeting.
·
Developed and
delivered Analogy’s feature presentation at the Design Automation Conference
(DAC), the industry's premier technical conference and trade-show.
Senior Design
Engineer, Analogy, Inc, Portland, OR 1986
- 1994
·
Facilitated growth of
Portland Center from a start-up of 10, without a customer to a growing
international company of 135 with a diversified customer base including the
leaders of the aerospace, automotive, power conversion and medical
industries.
·
Conceived, created,
and brought to market a library of advanced test and measurement models to add
strategic competitive advantages to Analogy’s Saber simulator.
·
Founded Consulting
Department, created the business plan, marketing collateral, and handled all
quotes and statements of work, grossing over $110,000 in my first year.
·
Founded the Customer
Support and Training Department.
·
Designed, wrote,
maintained and delivered training classes to over 1,000 engineers.
Applications
Engineer, Microcosm, Inc, Portland,
OR 1986
· Supported Microcosm’s line of in-circuit-emulators for all Intel microprocessors.
· Debugged product FPGAs.
Additional Training Experience
Contract Trainer Verifica, Portland, OR 2003
- 2004
·
Taught 3-day Specman
Jump Start Training Course and Introduction
to Specman Elite Verification Methods at Fortune 500 customer sites.
__________________________________
Contract Trainer Verisity, Mountain View, CA 2001
- 2002
·
Taught 3-day Specman
Basic Training Course at Verisity’s headquarters and Fortune 500 customer
sites.
Education
1986 BSEE DEGREE,
Oregon State University, Corvallis, OR
Papers
Portable Automatic In-Situ Testbench
Generation: A Case Study March,
2001 HDLCon 2001 Conference Co-authored
with Janick Bergeron, VP Engineering, Qualis Design Corp.
______________________________
Getting It Right:AMS Design and Verification Strategies October 2000 On-line
Symposium for Electrical Engineers
______________________________
AMS Design and Verification: On Time
Without Drama September
2000 Analog and Mixed-Signal
Applications Conference
______________________________
Avoiding Verilog Nightmares During
Verification. March 2000 Synopsys Users Group: SNUG 2000
Co-authored with David Black, Qualis Design Corp.